考試

module top;
wire A, B, C, D;
system_clk #50 clk1(D);
system_clk #100 clk2(C);
system_clk #200 clk3(B);
system_clk #400 clk4(A);
comparator c1 (A, B, C, D, F);
endmodule


module comparator(A, B, C, D, F);
input A, B, C, D;
output F;
wire f1,f2,f3,f4,f5,f6,c1,c2,c3,c4;
not (c1 ,A);
not (c2 ,B);
not (c3 ,C);
not (c4 ,D);

and (f1 ,c1 ,c2 ,D);
and (f2 ,c1 ,c3,D);
and (f3 ,c2 ,c3,D);
and (f4 ,A ,B ,c3,c4);
and (f5 ,A ,B ,C,D);
and (f6 ,c1 ,B ,C,c4);

or (F, f1, f2, f3, f4 ,f5, f6);
endmodule

module system_clk(clk);
parameter period=100;
output clk;
reg clk;
initial
clk=0;
always
#(period/2)clk=~clk;
always@(posedge clk)
if($time>1000)
#(period-1)
$stop;
endmodule

考試專用

module top;
wire A, B, C, D;
system_clk #50 clk1(D);
system_clk #100 clk2(C);
system_clk #200 clk3(B);
system_clk #400 clk4(A);
comparator c1 (A, B, C, D, F);
endmodule


module comparator(A, B, C, D, F);
input A, B, C, D;
output F;
wire f1,f2,f3,f4,c1,c2,c3,c4;
not (c1 ,A);
not (c2 ,B);
not (c3 ,C);
not (c4 ,D);

and (f1 ,c1 ,c2 ,c3);
and (f2 ,D ,c1);
and (f3 ,c3 ,A ,D);
and (f4 ,A ,c4 ,C);

or (F, f1, f2, f3, f4);
endmodule

module system_clk(clk);
parameter period=100;
output clk;
reg clk;
initial
clk=0;
always
#(period/2)clk=~clk;
always@(posedge clk)
if($time>1000)
#(period-1)
$stop;
endmodule